1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage system and particularly to a flash (chip erase) rope EEPROS circuit.
2. Description of the Related Art
In the accompanying drawings, FIG. 16 shows a flash type EEPROM circuit constructed in accordance with the prior art, which is illustrated as being of four-memory-transistor arrangement for simplicity.
As can be seen from FIG. 16. the flash EEPROM circuit comprises four memory transistors 1-4 which have source regions connected to a source line SL. The source line SL is connected to N- and P-channel transistors 11 and 12. The gate electrode of the N-channel transistor 11 receives an inverted erase signal while the gate electrode of the P-channel transistor 12 receives an inverted erase signal through an interface circuit 88. The interface circuit 88 functions to convert a fluctuation of input voltage at Vdd-GND into a fluctuation of output voltage at Vpp-GND.
The control gate electrodes of the memory transistors 1-4 are connected respectively to word line WL1 or WL2 while the drain regions of the memory transistors 1-4 are connected respectively to bit line BL1 or BL2.
Address signals are inputted to X- and Y-decoders 92 and 94 through an address buffer 90. In response to this, the X-decoder 92 generates word line signals to the word lines WL1 and WL2 while the Y-decoder 94 generates Y-decoder signals which are in turn outputted therefrom to a bit line control circuit 95 and sense amplifier 96.
The bit line control circuit 95 is responsive to the Y-decoder signals to control the writing of data. More particularly, the bit line control circuit 95 writes data signals inputted through the data butter 98 in the memory transistors 1-4 at addresses represented by the Y-decoder signals. The bit line control circuit 95 further controls the erasing and reading-out at the memory transistors 1-4.
On the other hand, the sense amplifier 96 reads out data stored in the memory transistors 1-4 using the Y-decoder signals as addresses. The read dare are then outputted, as data signals, tram the sense amplifier 96 to any external unit through the data buffer 98.
The operation of such a prior art system will now be described with reference to FIG. 17 which illustrates a truth table.
The writing operation will first be described. In the writing operation, erase signals are net at GND level to place the transistors 11 and 12 respectively in ON and OFF states. Thus, the source line SL is cat at GND level, as shown in FIG. 17. When the writing operation in to be carried out for the memory transistor 1, the word and bit lines WL1 and BL1 are set at high voltage Vpp level (e.g. 10-12 volts) and WL2 and BL2 are set at open level.
Under the above setting, the control gate electrode and drain region of only the memory transistor 1 are simultaneously placed at Voltage of Vpp level to generate a channel current. As a result, hot electrons are produced at the drain resign edge to inject electrons into the floating gate electrode. This causes the writing operation to be carried out for the memory transistor 1 so that data "0" will be stored therein. On the other hand, no channel current is produced in the other memory transistors 2-4 since the voltages at their control gate electrodes and drain regions are not simultaneously placed at Vpp level. Therefore, the writing operation will not be carried out for the memory transistors 2-4.
Next, the erasing operation Will be described. In the erasing operation, erase signals are set at VDD level to turn the transistors 11 and 12 respectively off and on. The source line SL is thus set at Vpp level, as shown in FIG. 17. Under such a situation, further, the word lines WL1 and WL2 are set at GND level while the bit lines BL1 and BL2 are set at Open level.
Under the above setting, the source regions of the memory transistors 1-4 will be set at Vpp level while the floating gate electrodes thereof will be set at GND level. Therefore, a tunnel current will be generated between the floating gate electrode and the source region in each memory transistor. As a result, electrons will be released from the floating gate electrode to the source region to perform the erasing operation.
The reading operation will be described. In the reading operation, erase signals are set at GND level to turn the transistors 11 and 12 respectively on and off. The source line SL is thus set at GND level, as shown in FIG. 17. When data is to be read out from the memory transistor 1, the word lines WL1 is set at VDD level; the bit line BL1 is set at read-out level Vred which is a positive voltage (e.g. 1 volt) ; the word line WL2 is set at GND level: and the bit line BL2 is set at Open level.
Under the above searing, only the memory transistor 1 will have the control gate electrode of VDD level, the drain region of Vred level and the source region of GND level. When the writing operation has been carried out for the memory transistor 1 or when data "0" has been stored in the memory transistor 1, the drain current will not flow in the bit line BL1. On the contrary, when the writing operation has not been carried our for the memory transistor 1 or when data "1" has been stored in the memory transistor 1, the drain current will flow in the bit line BL1. Therefore, the stored data can be read out by detecting the drain current at the sense amplifier.
During the writing, erasing and reading operations, the X-decoder 92 and bit line control circuit 95 are controlled in operation by the write, read, and erase signals.
The prior art raises a problem in that the electrons are excessively released to make the threshold voltage of the memory transistor negative or to produce overerasing in the erasing operation.
It is now assumed that the memory transistor 3 has been overerased. It is also assumed that the writing operation has stored data "0" transistor 1. If data is reed out from the memory transistor 1 under such a condition, any current ought not to flow through the bit line BL1 since the data "0" has been stored in the memory transistor 1. If the memory transistor 3 has been overerased, however, the drain current will flow at the bit line BL1 even though the control gale electrode is set at GND level, as shown in FIG. 16. The drain current causes the sense amplifier 96 to be subjected to malfunction, leading to wrong judgment that the data "1" has been stored in the memory transistor 1. As a result, the reading operation becomes false.
One of techniques for preventing such an overerasing is described In Japanese Patent Application Lald-Open No. Hei 1-294297. The technique detects an electric current flowing through a memory transistor during the erasing operation. If the current is detected, the transistor providing the erasing voltage is turned off to stop the erasing operation.
This technique is disadvantageous in that when a memory transistor is overerased, the erasing operation to the other memory transistors will also be stooped. This reduces the lower limit of operation margin in the other memory transistors
Another technique for preventing the overerasing is a technique known as a verifying operation that is described in Japanese Patent Application Laid-Open No. Bei 4-3395, for example. The verifying operation monitors the threshold voltages in all the memory transistors at all times after the erasing operation. If the threshold voltages in all the memory transistors are equal to or lower than a preselected verify voltage, it in judged that a proper erasing operation has been carried our for each of the memory transistors. At this time, the subsequent erasing operations will be interrupted. On the other hand, if the threshold voltage in even only one memory transistor is higher than the verify voltage, it is judged that the erasing operation has not properly been carried out. After the erasing operation has again been performed, the verifying operation is again carried out. The verifying and erasing operations will be repeated until all the memory transistors are properly erased.
However, the verifying operation has such a problem that any memory transistor having a higher erasing speed or an increased shift of threshold voltage to the negative direction during the erasing operation cannot be prevented from being overerased.
Further, the flash type EEPROM circuit of the prior art has problem in that the erasing operation requires more current flowing in the source line SL since it is of chin erase type or of block erase type. Therefore, the power supply ability of an internal voltage increasing circuit for supplying a high voltage VPP to the source line SL is limited to cause restriction of the capacity of the memory or supple of the high voltage VPP from the exterior of the semiconductor chip These problems were large obstructions on low voltage operation and on soluble voltage power supply operation.